The future of AI compute is being built on Arm. AI continues to transform every major market — from the largest datacenters to the smallest devices, such as earbuds — intensifying the demands on ...

HSINCHU, Taiwan, R.O.C., May 13, 2025 – The TSMC (TWSE: 2330, NYSE: TSM) Board of Directors today held a meeting, which passed the following resolutions: ...

This paper presents a new interface between the two main chips typically found in Wireless LAN (WLAN) devices: the digital baseband part (BB) and the radio transceiver part (RF). This interface is a ...

While developing large-sized chips, “divide & conquer” techniques are used. This involves partitioning the design, implementing each block individually, and stitching them together at the top level.

Static Timing Analysis (STA) is a key factor to validate while manufacturing a chip, where each design must go for setup and hold validation. In today’s era, technology nodes are shrinking and ...

The latest DDR4 SDRAM memory standard offers significant performance benefits for SoC designers. Graham Allan, senior product marketing manager for DDR at Synopsys, discusses some of the challenges ...

RISC-V is a general-purpose license-free open Instruction Set Architecture [ISA] with multiple extensions. It is an ISA separated into a small base integer ISA, usable as a base for customized ...

Structural coverage analysis is a method to ensure RBTs parse the code structure to verify every line of code for its correctness. RBTCA is used to determine the efficiency our tests verifying ...

In today’s deep sub-micron technology nodes like 16nm, 7nm & beyond, there is a huge challenge for accurate static timing calculation. Ever increasing routing congestion, thin metal layers and ...

Streams of data from higher-speed sensors pose throughput and latency challenges for designers. However, optimizing a design for those criteria can come at the expense of increased power consumption ...

This paper aims to share practical experience regarding building a power-optimized clock tree, determining the optimum targets for clock tree synthesis (CTS) and monitoring the quality of results (QoR ...

Over the past decade, we have seen generations of new products with increasingly sophisticated display feature sets. Each new generation pushes the boundaries of display technology even further with ...