Electronics Weekly

Imec develops die-to-wafer bond process with 2µm pad pitch

Imec has developed a Cu-to-Cu and SiCN-to-SiCN die-to-wafer bonding process resulting in a Cu bond pad pitch of only 2µm at <350nm die-to-wafer overlay error, achieving good electrical yield. Such ...
AZOM

Curved Shapes with Mask Wafer Co-Optimization

One of the main challenges in developing semiconductor chip technology is making electronic components smaller and more effective. This difficulty is most noticeable in lithography, which is the ...
Semiconductor Engineering

Hunting For Macro Defects

Detecting macro-defects early in the wafer processing flow is vital for yield and process improvement, and it is driving innovations in both inspection techniques and wafer test map analysis. At the ...
pv magazine International

Longi, ANU develop gettering-based process to improve n-type wafer quality

The Chinese module maker and the Australian National University utilized phosphorus diffusion gettering and another defect mitigation strategy to improve the quality of n-type wafers. The proposed ...
Business Wire

1366 Technologies and Hanwha Q CELLS Partner on World’s First Factory to Feature Direct Wafer® Manufacturing Process

BEDFORD, Mass. & SEOUL, South Korea--(BUSINESS WIRE)--Silicon wafer manufacturer 1366 Technologies together with its strategic partners, Hanwha Q CELLS Malaysia Sdn. Bhd. and parent company Hanwha Q ...
Digi Times

Boosting both capacity and yield, iST offers complete backend wafer process services for power semiconductor devices

Power consumption is a crucial consideration for all types of electronics. As critical power components used in a wide range of electronic products, power MOSFET and other types of power semiconductor ...