Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
Electronic Design

Marvin Test Solutions expands user-programmable PXIe FPGA product line

IRVINE, CA—Marvin Test Solutions, Inc., a provider of globally-deployed innovative test solutions for military, aerospace, and manufacturing organizations, has announced the release of the new GX3800e ...
EDN

Internal test in FPGA design

http://www.xilinx.comAs the density of field-programmable-gate arrays (FPGAs) continues to increase, engineers are challenged to come up with ways to test and verify ...